Which of the circuit is described by following VHDL code? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY my_func IS PORT(x, a, b : IN std_logic; q : OUT std_logic); END my_func; ARCHITECTURE behavior OF my_func IS SIGNAL s : INTEGER; BEGIN WITH s SELECT q <= a AFTER 10 ns WHEN 0; b AFTER 10 ns WHEN 1; s <= 0 WHEN x = ‘0’ ELSE 1 WHEN x = ‘1’; END behavior;

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Question: Which of the circuit is described by following VHDL code? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY my_func IS PORT(x, a, b : IN std_logic; q : OUT std_logic); END my_func; ARCHITECTURE behavior OF my_func IS SIGNAL s : INTEGER; BEGIN WITH s SELECT q <= a AFTER 10 ns WHEN 0; b AFTER 10 ns WHEN 1; s <= 0 WHEN x = ‘0’ ELSE 1 WHEN x = ‘1’; END behavior;

1.AND gate

2.OR gate

3.MUX 2:1

4.DEMUX 1:2

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  1. Which of the circuit is described by following VHDL code? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY my_func IS PORT(x, a, b : IN std_logic; q : OUT std_logic); END my_func; ARCHITECTURE behavior OF my_func IS SIGNAL s : INTEGER; BEGIN WITH s SELECT q <= a AFTER 10 ns WHEN 0; b AFTER 10 ns WHEN 1; s <= 0 WHEN x = ‘0’ ELSE 1 WHEN x = ‘1’; END behavior;
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