Refer to the VHDL code given below, which of the following line has error? Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’; Line 2: SIGNAL a: BIT; Line 3: SIGNAL b: STD_LOGIC; Line 4: SIGNAL c: my_logic; Line 5: b<=a; Line 6: b<=c;

  1. Home

Question:Refer to the VHDL code given below, which of the following line has error? Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’; Line 2: SIGNAL a: BIT; Line 3: SIGNAL b: STD_LOGIC; Line 4: SIGNAL c: my_logic; Line 5: b<=a; Line 6: b<=c;

1.Line 1

2. Line 4

3. Line 5

4. Line 6

Posted by R4R Team
  1. Refer to the VHDL code given below, which of the following line has error? Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’; Line 2: SIGNAL a: BIT; Line 3: SIGNAL b: STD_LOGIC; Line 4: SIGNAL c: my_logic; Line 5: b<=a; Line 6: b<=c;
Search
R4R Team
R4Rin Top Tutorials are Core Java,Hibernate ,Spring,Sturts.The content on R4R.in website is done by expert team not only with the help of books but along with the strong professional knowledge in all context like coding,designing, marketing,etc!