What will be the value of y after the execution of the following VHDL code? Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; … SIGNAL m : UNSIGNED (3 DOWNTO 0); SIGNAL n : UNSIGNED (3 DOWNTO 0); SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0); y <=CONV_STD_LOGIC_VECTOR ((m+n), 8);

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Question:What will be the value of y after the execution of the following VHDL code? Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; … SIGNAL m : UNSIGNED (3 DOWNTO 0); SIGNAL n : UNSIGNED (3 DOWNTO 0); SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0); y <=CONV_STD_LOGIC_VECTOR ((m+n), 8);

1.8- bit STD_LOGIC_VECTOR m+n

2.8- bit UNSIGNED m+n

3.4- bit STD_LOGIC m+n

4.Error

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  1. What will be the value of y after the execution of the following VHDL code? Library ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; … SIGNAL m : UNSIGNED (3 DOWNTO 0); SIGNAL n : UNSIGNED (3 DOWNTO 0); SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0); y <=CONV_STD_LOGIC_VECTOR ((m+n), 8);
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