In the VHDL code given below, which delay model is used? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY buffer IS PORT(a : IN STD_LOGIC; b : OUT STD_LOGIC); END buffer; ARCHITECTURE buf OF buffer IS BEGIN b <= a AFTER 20 ns; END buf;

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Question:In the VHDL code given below, which delay model is used? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY buffer IS PORT(a : IN STD_LOGIC; b : OUT STD_LOGIC); END buffer; ARCHITECTURE buf OF buffer IS BEGIN b <= a AFTER 20 ns; END buf;

1.Simulation delta model

2.Transport delay model

3.Inertial delay model

4.Multiple driver delay model

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  1. In the VHDL code given below, which delay model is used? LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY buffer IS PORT(a : IN STD_LOGIC; b : OUT STD_LOGIC); END buffer; ARCHITECTURE buf OF buffer IS BEGIN b <= a AFTER 20 ns; END buf;
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