In the VHDL code given below, what will be the error at the time of compilation? TYPE my_int IS INTEGER RANGE -32 TO 32; TYPE other_int IS INTEGER RANGE 0 TO 100; SIGNAL x : my_int; SIGNAL y : other_int; y <= x + 2;

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Question:In the VHDL code given below, what will be the error at the time of compilation? TYPE my_int IS INTEGER RANGE -32 TO 32; TYPE other_int IS INTEGER RANGE 0 TO 100; SIGNAL x : my_int; SIGNAL y : other_int; y <= x + 2;

1.Type mismatch

2.Syntax problem

3.No declaration

4.Can’t compile

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  1. In the VHDL code given below, what will be the error at the time of compilation? TYPE my_int IS INTEGER RANGE -32 TO 32; TYPE other_int IS INTEGER RANGE 0 TO 100; SIGNAL x : my_int; SIGNAL y : other_int; y <= x + 2;
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